This invention relates generally to statistical timing analysis of integrated circuits, and more particularly to timing closure on multiple selective corners in a single statistical timing run of an integrated circuit design.
Timing analysis is used to verify integrated circuit designs and analyze circuit performance. Timing of integrated circuits may vary due to the effects of environmental and process variation. Example sources of variation include, but are not limited to, voltage, metal thickness, temperature, transistor channel length, transistor threshold voltage, gate oxide thickness and other process controlled performance changing parameters. The traditional timing methodology that has been used to handle such variability in an integrated circuit includes conducting multiple static timing analyses at different “cases” or “corners” to determine the spread of performance of the circuit under these variations. A corner refers to a set of process parameters/environment conditions (hereinafter “parameters”) that cause variations in the static timing analysis of an integrated circuit. Corners may include, for example, a “best case” corner that provides the fastest path delay between two particular nodes in a circuit path or “worst case” corner that provides the slowest path delay between two particular nodes in a circuit path. Bounding the timing for each possible corner will lead to an unmanageable number of timing runs (i.e., 2N set of runs for N parameters that can take on two values) because of the numerous independent and significant sources of variation. This unmanageable number of timing runs makes it difficult to get timing closure on an integrated circuit design.
Several approaches have been implemented to perform such multiple-corner static timing analyses. One approach that has been implemented to perform a multiple-corner static timing analysis includes performing multiple discrete timing runs in one or more computers and merging the multiple single timing results. Because there are so many parameters it is still difficult to obtain timing closure despite the use of one or more computers. Another approach includes using a Variation-Aware Timing (VAT) methodology that uses a reduced set of timing runs to perform a multiple-corner timing analysis in the presence of parameter variation. For example, hundreds of traditional, discrete timing runs that would have been previously required to account for all parameter variations can be reduced to only four timing runs for a typical application specific integrated circuit (ASIC) by using the VAT methodology. However, the VAT methodology still does not provide full chip coverage even though all timing corners are analyzed as it suffers from a trade-off between run-time and more path coverage due to its path-based inherence.
In light of the issues associated with a corner static timing analysis performed on one or more computers and the VAT methodology, a statistical timing analysis has been used as a way to accurately account for device, interconnect and process and environment variations. Statistical timing reduces the excessive number of analysis runs required for timing closure and minimizes pessimism (i.e., requiring additional margin for a signal to become stable earlier or remain stable later than would be required against another signal or absolute time) compared to the above-noted techniques. During statistical timing analysis, timing quantities such as delays, arrival times and slacks are not treated as single numbers, but rather as probability distributions. Thus, the full probability distribution of the performance of the integrated circuit under the influence of variations is predicted by a single timing run. As a result, this methodology can guarantee integrated circuit timing across the full parameter space including all corners, even non-physical corners.
As parameter control has become more and more difficult, timing closure over the full parameter distribution has become quite challenging. Because doing timing analysis on an integrated circuit chip is not the same as performing timing closure on the integrated circuit. Determining timing slacks in the full parameter space does not mean that the slacks need to be fixed in the full parameter space. A chip can achieve required performance under different conditions. For example, in a Process-Voltage-Temperature (PVT) space, an integrated circuit chip fabricated at the “fast” end of a process distribution may achieve required performance at one fixed temperature and voltage corner, while a chip fabricated at the “slow” end of a process distribution may achieve required performance at another fixed temperature and voltage corner. So, manufactured integrated circuit chips can be sorted into different bins based on whether they were fabricated at either the “slow” end or the “fast” end of a process distribution. Then an optimal temperature and voltage supply for operating the chips in each bin is determined. Based on that technique, it is appropriate to close integrated circuit chip timing only on a subset of the full parameter space.